As described in the above-referenced '402 application, to accommodate voice and data signaling requirements of various communication service providers and their customers, manufacturers of digital communication equipment currently offer integrated access devices (IADs). These devices allow a user to interface multiple types of digital voice and data signaling circuits with a (wide area) communication network. Unfortunately, conventional IAD designs have been constrained by the lack or limited availability of reasonably priced and versatile communication control processors. A fundamental shortcoming of these conventional controller chips is the fact that they are digital signal processor (DSP)-based, consume large amounts of power, and are procurable from essentially one semiconductor fabrication source. Being DSP-based also means that the functionality of an IAD using such control chips is heavily dependent on embedded software. In addition, these chips have only a small number voice and data interface ports, which are typically permanently dedicated to specified signaling modes, thereby limiting their flexibility and efficiency in the face of dynamic signaling requirements.
In accordance with the invention disclosed in the '402 application, shortcomings of conventional IADs are effectively remedied by a ‘DSP-less’ IAD architecture, that is configured as a dual PHY-based signal transport application specific integrated circuit (ASIC), and is operative to provide significantly enhanced interfacing flexibility for multiple and diverse types of digital communication signaling. More particularly, as shown in FIG. 1, which diagrammatically illustrates the overall configuration of that architecture, the IAD disclosed in the '402 application comprises a multi-protocol communication interface (MCI)100, and an associated host network processor 200.
The multi-protocol communication interface 100 performs digital communication signaling interface functions in accordance with supervisory control inputs supplied from the host network processor 200 by way of a generic, host processor interface 160. In order to provide signal transport and network processor control interconnectivity, the multi-protocol communication interface 100 contains a plurality of signaling interface ports P1-P6, of which ports P1-P5 interface digital communication signals with the host network processor 200 and various external communication paths, and port P6 of which interfaces control signals with the processor 200.
A first, wide area communication network port P1 terminates a wide area network (WAN) 10 with a first port 111 of a conventional bidirectional digital cross-connect switch (XCS) 110, and provides both ATM and high level data link control (HDLC) connectivity with the WAN 10. A second, voice TDM or TDM2 port P2 terminates a second port 112 of the digital cross-connect switch with a voice TDM circuit 20, and provides digital transport connection to various TDM communication transceivers, such as analog codecs and T1 (including fractional T1) transceivers. Port P2 may be configured as a conventional TDM mode port and supports standard TDM control parameters, including Frame Sync, transmit and receive clock and data signals. In addition, port P2 is coupled to an adaptive clocking unit 260, which is operative during ATM mode operational mode to adjust clock and frame sync to incoming cell delivery timing over an internal TDM bus 210 from a bidirectional voice gateway 150.
Installed within the internal TDM bus 210 is a cascaded arrangement of a TDM transport path-cascaded echo canceler 270 and ADPCM voice compression operator 280, which implement G.726 ADPCM voice compression and G.168 echo cancellation by operating directly on the TDM encoded voice stream. Producing a processed digitized voice signal stream in this manner relieves the host processor of having to use data bus cycles to download processed digitized voice samples. TDM bus 210 is also coupled to a dual tone multifrequency detector (DTMF) unit 250, which contains a plurality of DTMF detectors that may be selectively dedicated to tone sensing functions for signaling operations on the TDM bus.
A third, UTOPIA port P3 terminates a dual UTOPIA L2 PHY interface 130 with a byte-wide, ATM cell-based UTOPIA bus 30. This bus serves as the main ‘data’ or communication signal transport path with the host network processor. The dual UTOPIA L2 PHY interface 130 and its associated UTOPIA bus 30 operate at a very high clocking frequency (on the order of 25 MHz, which equates to an enhanced data transport rate on the order of 200 MBps) relative to network and terminal rates (which have data rates on the order of only 1.5-2.0 Mbps (e.g., a WAN rate of 2304 kpbs)). As such, signaling transport communications between the multi-protocol communication interface 100 and the host network processor 200 are effectively quasi-instantaneous, so that participation by the host network processor in the transport of both digitized voice and data communication signals over any of the routing paths among the signaling ports of the multi-protocol communication interface will not burden (slow down) the operational speed of any of the external communication circuits to which the IAD is ported.
The dual UTOPIA L2 PHY interface 130 contains two separate physical layer (PHY) portions (PHY0 for data, and PHY1 for voice), each PHY layer being byte-wide and containing separate transmit (TX) and receive (RX) buses. The PHY1 portion is dedicated to voice signaling and has the higher priority of the two PHY portions. PHY0 (associated with data transport) is the lower priority of the two portions. The voice PHY portion (PHY1) of the dual UTOPIA L2 PHY interface 130 is used for voice ATM cell transfers between bidirectional voice playout buffers of a multi-channel voice playout buffer unit 290 and the host network processor 200, and for ATM voice cell transfers between the host network processor 200 and the WAN via a voice WAN FIFO 330. The data PHY portion (PHY0) of the dual UTOPIA L2 PHY interface 130 is used for data ATM cell transfers between the host network processor and sets of TX and RX data FIFOs, serving the WAN and an auxiliary V.35 circuit path.
A fourth, NxPORT P4 of the multi-protocol communication interface 100 terminates an external port 143 of a bidirectional multiplexer (mux/demux) 140 with an auxiliary (Nx56/64) digital communication path 40, over which non cell-based (e.g., V.35) digital communications are conducted with an auxiliary digital communication device. The fifth communication port P5 is a TDM legacy port, that terminates a first port 151 of the gateway 150 with a legacy voice TDM communication link 50. As pointed out above, gateway 150 provides TDM connectivity with a TDM bus 210 containing the TDM transport path-cascaded echo canceler 270 and ADPCM voice compression operator 280.
The TDM bus 210 is further coupled to TDM voice port 113 of bidirectional digital cross-connect switch (XCS) 110. This internal TDM voice interconnect path makes the multi-protocol communication interface compatible with legacy IAD architectures, such as those which employ a Motorola 860 processor. The TDM legacy port PS supports these architectures where TDM-IN and TDM-OUT interfacing are used. In such a legacy TDM mode, port PS is TDM-coupled to port P2, by-passing ATM signal processing paths that use dual UTOPIA L2 PHY interface 130 and UTOPIA bus 30 to the host network processor.
A second port 152 of the TDM voice gateway 150 is coupled over a link 212 to port 291 of bidirectional voice playout buffers of the multi-channel voice playout buffer unit 290. For the case of 32 voice channels, as a non-limiting example, the voice playout buffer unit 290 contains 32 channels of bidirectional first-in, first-out registers (FIFOs). All of these channels operate independently and concurrently. Each of these FIFOs is sized (e.g., has a 64 byte capacity) to store the voice payload of an ATM cell (44 bytes), as well as accommodate transport delay to and from the host network processor, and thereby allow for an effectively continuous interfacing/flow and conversion of TDM communication signals on the TDM bus 210 with ATM cells interfaced with dual UTOPIA L2 PHY interface 130 over a full duplex ATM cell bus 214 therebetween. The remaining port P6 of the multi-protocol communication interface terminates a control signal bus 60 with a generic, host processor interface (HPI) 160, through which control signals are interfaced with the HNP 200 for configuring and managing the functionality of the multi-protocol communication interface.
The digital cross-connect switch (XCS) 110, which may be of conventional construction, provides first and second external communication signaling port terminations 111/P1 and 112/P2 with the WAN 10 and voice TDM circuit 20, respectively. In addition to its two external ports 111 and 112, XCS 110 includes a third, TDM voice port 113, through which TDM voice circuit 20 is coupled to the internal TDM bus 210. XCS 110 has a fourth, ATM port 114, and a fifth, HDLC port 115, which respectively provide connectivity between the WAN port 111 and a WAN ATM transceiver 220, and a WAN HDLC transceiver 230. The digital cross connect switch 110 further includes a sixth, Nx port 116, that is coupled to a first internal port 141 of mux/demux 140. A second internal port 142 of mux/demux 140 is coupled to an NxPORT HDLC transceiver 240.
There are two modes of operation of the digital XCS 110: direct DS0-mapping mode; and ATM/HDLC transceiver interface mode. In DS0-mapping mode, the internal dual ATM PHY conversion and transport functionality of the MCI is effectively bypassed; instead, DS0 time slots on the voice TDM link 20 at port 112 are directly mappable to port 111 and WAN 10, based upon a user-controlled mapping scheme. In addition, DS0 time slots on the voice TDM link 20 at port 112 are directly mappable to the voice port 113, so that they may be coupled to the internal TDM bus 210. DS0 time slots at port 112 may also be directly mapped via port 116 to port 141 of Nx mux/demux 140 for Nx56/64 clear channel (V.35) operation. As noted above, DTMF detector unit 250 coupled to internal TDM bus 210 may be used to analyze DTMF and dial tone signals.
In ATM/HDLC transceiver interface mode, XCS 110 couples the WAN port 111 to the appropriate one of ATM and HDLC transceiver ports 114 and 115, which are respectively coupled to WAN ATM transceiver 220 and WAN HDLC transceiver 230. Considering first, ATM mode communications, in the receive direction (incoming from the WAN toward the network processor), the WAN ATM transceiver 220 is configured to interface, over an eight bit wide receive bus 222 to a receive (RX) FIFO 310, incoming ATM cells that have been coupled thereto via port 114 of XCS 110. As a non-limiting example, RX FIFO 310 may have a relatively small depth (e.g. 128 bytes, which accommodates two ATM cells or 106 bytes) due to the considerably higher speed of the UTOPIA L2 PHY bus. ATM cells supplied to RX FIFO 310 are output via a permanent virtual circuit (PVC) router 120 to the data (PHY0) portion of the dual UTOPIA L2 PHY interface 130, for transport over UTOPIA bus 30 to the network processor.
The PVC router 120 is preferably implemented using multibit table entries in internal memory to control or ‘steer’ the flow of ATM data cells of various virtual circuits within the MCI for voice and data signaling transport. For a 32 channel implementation, the PVC routing table supports 32 entries for transmit and 32 entries for receive, and specifies to/from which interface the ATM cell of interest is delivered. In a customary manner, PVC router 120 is configured to analyze the contents of a respective packet presented to it and then selectively route the packet to the appropriate output port based upon the results of that analysis.
For incoming ATM voice cells from the WAN 10, routing to the network processor is from the RX FIFO 310 to the PHY1 port of the dual UTOPIA L2 PHY interface 130, whereas transmitted WAN voice routing from the processor is from the PHY1 portion of dual PHY layer to the voice WAN FIFO 330. For incoming voice calls from the TDM2 network 20, routing is from the cell bus 214 serving the voice playout buffer unit 290 to the PHY1 portion of interface 130, whereas outgoing voice calls to the TDM2 network 20, routing is from the PHY1 portion of interface 130 over the cell bus 214 to the voice playout buffer unit 290.
For ATM data cells received via ATM transceiver 220 from the WAN 10, routing to the network processor is from the RX FIFO 310 to the PHY0 port of the dual UTOPIA L2 PHY interface 130, whereas transmitted WAN data routing from the processor is from the PHY0 portion of dual PHY layer to the WAN DTX FIFO 320 and to WAN ATM transceiver 220. For HDLC traffic received via HDLC receiver 230 from the WAN 10, routing to the network processor is from the RX FIFO 310 to the PHY0 port of the dual UTOPIA L2 PHY interface 130, whereas transmitted WAN data routing from the processor is from the PHY0 portion of the dual PHY layer to the WAN DTX FIFO 320 and to HDLC transceiver 230.
For incoming auxiliary V.35 routing, the PVC router 120 directs data entries in the V.35 RX FIFO 340 to the PHY0 portion of the dual UTOPIA L2 PHY interface 130; for outgoing auxiliary V.35 routing, PVC router 120 directs the AAL5 encapsulated data from the PHY0 portion of the dual UTOPIA L2 PHY interface 130 into the V.35 TX FIFO 350.
As described briefly above, the voice playout buffer unit 290 contains a plurality (32 in the present example) of voice channel-associated bidirectional FIFOs, each of which has a (64 byte) capacity that is sufficient to store a standard (44-byte) voice payload of a full ATM cell, while also providing extra capacity to accommodate expected worst case transport delay to and from the host network processor. This ensures effectively continuous interfacing/flow and conversion of TDM communication voice data on the TDM bus 210 with ATM cells that are interfaced with dual UTOPIA L2 PHY interface 130 over the full duplex ATM cell bus 214.
This may be understood by reference to FIG. 2, which diagrammatically illustrates an array of 32 (64 byte) bidirectional playout buffers 400-0, 400-1, . . . , 400-31 that make up the voice playout buffer unit 290. For transmitting and receiving ATM cells via the full duplex ATM cell bus, a respective voice playout buffer 400-i is coupled to an ATM cell port 292. For interfacing TDM data with the TDM bus, a respective voice playout buffer 400-i is coupled to a TDM port 291.
In operation, for the flow of TDM voice traffic received from the TDM bus 210 (as sourced from the TDM2 port P2 that terminates port 112 of the digital cross-connect switch with voice TDM circuit 20), let it be initially assumed that all of the voice playout buffers 400-i are cleared or reset. As such, received TDM voice traffic from the TDM bus will be written into successive byte locations of a respective playout buffer 400-i, beginning with the lowermost or ‘0’th byte location (as pointed to by a (bit-oriented) voice pointer (VP)), which is incremented through successive storage locations of the voice playout buffer, at the rate of the received data clock.
As successively received TDM voice data is written into successive bytes/locations of respective voice playout buffer channels from the TDM bus, the voice pointer (VP) will eventually point to the 43rd byte location of the highest numbered channel for which data is stored. If all 32 channels have received voice data, this would correspond to byte 43 of buffer 400-31. If less than all 32 channels are used, this would correspond to the highest numbered channel. For example, if channel 31 contained voice data, the highest numbered buffer in use would be buffer 400-31; otherwise, if channel 31 is not used, the voice pointer would point to the 43rd byte of the highest numbered channel (channel 30 or less) for which voice data is stored. In response to the loading of the 44th byte into the highest numbered buffer for which data is stored, all channels are encapsulated with ATM headers as 53 byte ATM cells and then ‘burst’-routed via PVC 120 and the dual PHY layer 130 to the host processor for delivery to a downstream WAN circuit.
The fact that each individual voice playout buffer 400-i has a sixty-four byte capacity means that, for a 44 byte data field of a respective 53 byte ATM cell, there is a twenty-byte window within which the host processor must return a response ATM voice packet for the POTS channel of interest. ATM encapsulation of a respective 44 byte data field includes a four byte ATM Adaptation Layer 2 (AAL2) header, a HEC byte and a four byte ATM header, to realize a standard 53 byte ATM cell. Within the AAL2 header, the channel identification byte (CID) byte may be made programmable, so as to provide selective mapping to timeslots of a TDM frame, and thereby accommodate variations among different vendor equipments.
In the return direction from the host processor, the ATM overhead bits are stripped off and the remaining 44 bytes of voice payload data are written into the successive locations of the playout buffer, as pointed to by a cell pointer (CP), beginning with the first byte of the 44 bytes that had just been burst out over the PHY bus to the processor. So long as the voice pointer (VP), which has been and continues to be incremented at the relatively slower TDM rate, has not reached the end (byte location 63) of the playout buffer and begun ‘wrapping around’ to the lowest byte location, and with the contents of the first 44 byte locations of the playout buffer having been read out to the processor and therefore stale, return voice cell data from the processor may be written into those same (stale data) byte locations (0-43) of the playout buffer from which the previous burst was received.
Thus, if the host processor has (and due to its considerably higher speed is expected to have) returned a response ATM voice cell containing 44 bytes of TDM data to the playout buffer, before the end of the twenty cell window of the playout buffer has been reached, there can expected to be some byte differential (one to twenty bytes, in the present example of a 64 byte capacity playout buffer) between the current location of the voice pointer (VP) and that of the cell pointer (CP). This flexibility offered by the practical size of the voice playout buffer greatly reduces the cost and complexity of the digitized voice transport path. Namely, as long as this ‘turn-around’ differential remains within the twenty byte window, continuity of voice packet flow (with no overflow and no underflow) will be effectively maintained throughout a call. If a return cell is not ready to send, the host processor will resend the last transmitted cell, to maintain continuous voice cell flow.
As further described in the '402 application, the voice playout buffer employs a single write interrupt, in order to optimize DMA transfer efficiency of as many playout buffers (up to 32) that currently have data for the host processor. Namely, at this single interrupt, all active channels (up to 32 channels in the present example) of ATM cell data are transferred into processor memory under DMA control. The use of a single interrupt successfully addresses a number of issues dealing with loading of the host network processor.
In a typical packetized voice cell transfer, the associated host processor would customarily be interrupted every time a voice packet is ready for transmission. For a thirty two channel voice playout buffer, this would result in 32 interrupts to handle all 32 channels. The interrupt handler would then transfer responsibility for the voice packet to a resident software task. A significant problem with this approach is the fact that the processor is interrupted on a per-voice packet basis. Another problem is the need to handle each individual voice packet by a software task. These requirements entail a substantial consumption of host processing power, which could be used elsewhere to improve overall system performance.